Name
Abstract | ||
|---|---|---|
This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface with automatic test equipment through an optimized number of channels. They are well suited for SoC devices comprising both nonisolated cores, i.e., blocks that occasionally need to be tested simultaneously, and completely wrapped modules. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application schemes and are reported herein. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCAD.2012.2205385 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | Field | DocType |
scan-based test,low pin-count testing,embedded deterministic test,test scheduling,preemptive test application,test data reduction,soc device,soc design,bandwidth management,bandwidth allocation,test access mechanism,automatic test equipment,test scheduling algorithm,system on chip design,system-on-chip,embedded deterministic test based compression,wrapped modules,nonisolated cores,edt bandwidth management,test compression | Computer science,Electronic engineering,Test data,Computer engineering,Deterministic testing,Bandwidth management | Journal |
Volume | Issue | ISSN |
31 | 12 | 0278-0070 |
Citations | PageRank | References |
13 | 0.59 | 49 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jakub Janicki | 1 | 46 | 4.31 |
| Mark Kassab | 2 | 654 | 48.74 |
| Grzegorz Mrugalski | 3 | 501 | 35.90 |
| Nilanjan Mukherjee | 4 | 801 | 57.26 |
| Janusz Rajski | 5 | 2460 | 201.28 |
| Jerzy Tyszer | 6 | 838 | 74.98 |