Name
Abstract | ||
|---|---|---|
The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing a which uses a sorter as the main building block. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits which allow to improve previous results for multipliers based on a similar architecture. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ISCAS.1999.777872 | ISCAS (1) |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
2 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| E Rodriguez-Villegas | 1 | 103 | 19.22 |
| Maria J. Avedillo | 2 | 38 | 10.61 |
| José M. Quintana | 3 | 62 | 14.84 |
| Gloria Huertas | 4 | 74 | 13.29 |
| Adoración Rueda | 5 | 275 | 40.01 |