Name
Abstract | ||
|---|---|---|
This paper presents novel methods of enhancing test compression solutions for SoC designs. The ability of the proposed schemes to improve the encoding efficiency, test compression, and test time is accomplished by either appropriate selecting or laying out ATE channel injectors within EDT-based decompressors. The efficacy of new techniques with respect to test bandwidth management is demonstrated by running experiments on several industrial SoC designs and is reported herein. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ETS.2012.6233003 | European Test Symposium |
Keywords | Field | DocType |
scan-based designs,logic circuits,embedded deterministic test,encoding efficiency,bandwidth compression,bandwidth management,channel bandwidth management,system-on-chip,edt-based compressor,ate channel injector,bandwidth-aware test compression logic,test compression,test data compression,soc design,bandwidth,switches,system on a chip,encoding,multicore processing,phase shifter,system on chip | Logic gate,System on a chip,Computer science,Bandwidth compression,Communication channel,Electronic engineering,Real-time computing,Bandwidth (signal processing),Test compression,Bandwidth management,Embedded system,Encoding (memory) | Conference |
ISSN | ISBN | Citations |
1530-1877 | 978-1-4673-0695-9 | 8 |
PageRank | References | Authors |
0.49 | 24 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jakub Janicki | 1 | 46 | 4.31 |
| Jerzy Tyszer | 2 | 838 | 74.98 |
| Grzegorz Mrugalski | 3 | 501 | 35.90 |
| Janusz Rajski | 4 | 2460 | 201.28 |