Paper Info
Title
Meeting points: using thread criticality to adapt multicore hardware to parallel regions
Abstract
We present a novel mechanism, called meeting point thread characterization, to dynamically detect critical threads in a parallel region. We define the critical thread the one with the longest completion time in the parallel region. Knowing the criticality of each thread has many potential applications. In this work, we propose two applications: thread delaying for multi-core systems and thread balancing for simultaneous multi-threaded (SMT) cores. Thread delaying saves energy consumptions by running the core containing the critical thread at maximum frequency while scaling down the frequency and voltage of the cores containing non-critical threads. Thread balancing improves overall performance by giving higher priority to the critical thread in the issue queue of an SMT core. Our experiments on a detailed microprocessor simulator with the Recognition, Mining, and Synthesis applications from Intel research laboratory reveal that thread delaying can achieve energy savings up to more than 40% with negligible performance loss. Thread balancing can improve performance from 1% to 20%.
Year
DOI
Venue
2008
10.1145/1454115.1454149
PACT
Keywords
Field
DocType
meeting point thread characterization,negligible performance loss,thread criticality,smt core,critical thread,energy consumption,non-critical thread,thread balancing,overall performance,parallel region,thread delaying,multicore hardware,microarchitecture
Win32 Thread Information Block,Instruction set,Computer science,Parallel computing,Thread (computing),Real-time computing,Thread safety,Dynamic priority scheduling,Multi-core processor,Fiber (computer science),Microarchitecture
Conference
ISBN
Citations 
PageRank 
978-1-5090-3021-7
46
1.89
References 
Authors
23
6
Name
Order
Citations
PageRank
Qiong Cai11337.91
José González252635.85
Ryan Rakvic31518.96
Grigorios Magklis470245.64
Pedro Chaparro524817.27
Antonio González63178229.66