Name
Abstract | ||
|---|---|---|
This paper presents a concurrent soft-error resilience (CSER) scheme with features that aid manufacturing test, online debug, and defect tolerance. The proposed CSER scheme is based on the built-in soft-error resilience (BISER) technique. A BISER cell is redesigned into various robust CSER cells that provide slow-speed snapshot, manufacturing test, slow-speed signature analysis, and defect tolerance capabilities. The cell-level area, power, and performance overhead of the robust CSER cells were found to be generally within 1% to 22% of the BISER cell. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/VTS.2010.5469588 | VTS |
Keywords | Field | DocType |
online debug,slow-speed snapshot,defect tolerance capabilities,concurrent soft-error resilience,manufacturing test,biser,fault diagnosis,transient response,slow speed signature analysis,built-in soft-error resilience,cser,cell-level area,transient analysis,soft error,manufacturing,error correction,resilience,robustness | Psychological resilience,Transient response,Soft error,Computer science,Error detection and correction,Real-time computing,Electronic engineering,Robustness (computer science),Transient analysis,Snapshot (computer storage),Reliability engineering,Debugging | Conference |
ISSN | ISBN | Citations |
1093-0167 | 978-1-4244-6649-8 | 1 |
PageRank | References | Authors |
0.37 | 8 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Laung-terng Wang | 1 | 601 | 44.22 |
| Nur A. Touba | 2 | 1929 | 123.42 |
| Zhigang Jiang | 3 | 85 | 20.12 |
| Shianling Wu | 4 | 165 | 26.85 |
| Jiun-Lang Huang | 5 | 263 | 35.90 |
| James Chien-Mo Li | 6 | 187 | 27.16 |