Name
Abstract | ||
|---|---|---|
A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.4 × 1.4 mm2 in a 0.18-μm CMOS process and consumes 52 mW. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1093/ietfec/e91-a.2.497 | IEICE Transactions |
Keywords | DocType | Volume |
dual-modulus divider,down-spread spectrum clock generator,overall fractional division,division period,fractional division,nested fractional topology,frequency modulation,n divider,fractional phase-locked loop,fractional control circuit,dual-modulus divide-by,delay locked loop,delay lock loop,spread spectrum,phase lock loop | Journal | E91-A |
Issue | ISSN | Citations |
2 | 0916-8508 | 1 |
PageRank | References | Authors |
0.38 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yuan Yang | 1 | 227 | 36.15 |
| Chih-Hsiang Chang | 2 | 103 | 10.91 |
| Wen-Ger Wong | 3 | 19 | 1.68 |