Name
Abstract | ||
|---|---|---|
This paper presents a new scan-based BIST schemewhich achieves very high fault coverage without the deficienciesof previously proposed schemes. This approach utilizes scan orderand polarity in scan synthesis, effectively converting the scanchain into a ROM capable of storing some "center" patterns fromwhich the other vectors are derived by randomly complementingsome of their coordinates. Experimental results demonstrate that avery high fault coverage can be obtained without any modificationof the mission logic, no test data to store and very simple BISThardware which does not depend on the size of the circuit. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1145/266021.266203 | DAC |
Keywords | Field | DocType |
high fault coverage,random pattern generation,approach utilizes,test data,new scan-based bist schemewhich,mission logic,orderand polarity,avery high fault coverage,simple bisthardware,automatic test pattern generation,logic design,covering problems,autocorrelation,degradation,integer linear programming,hardware,fault coverage | Logic synthesis,Stuck-at fault,Boundary scan,Automatic test pattern generation,Fault coverage,Computer science,Algorithm,Scan chain,Electronic engineering,Real-time computing,Test data,Test compression | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-89791-920-3 | 22 |
PageRank | References | Authors |
1.60 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. H. Tsai | 1 | 22 | 1.60 |
| S. Hellebrand | 2 | 107 | 12.02 |
| J. Rajski | 3 | 985 | 63.36 |
| Malgorzata Marek-Sadowska | 4 | 2272 | 213.72 |