Name
Title | ||
|---|---|---|
Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs |
Abstract | ||
|---|---|---|
Dynamicreconfigurationisapromisingapproachtoenhance the resource efficiency of FPGAs beyond the current pos- sibilities. One of the main prerequisites for its implemen- tation is a communication infrastructure that enables data transfer between the hardware modules that are placed on the FPGA at run-time. In this paper we present a new com- munication macro for Xilinx FPGAs that considers the spe- cial requirements of these systems. While most solutions that were presented so far enable basic communication be- tween a low number of hardware modules at fixed positions, our approach implements an infrastructure that allows free placement of hardware modules at run-time. Methodolo- gies like 2D-placement of modules, which were analyzed mainly in theory so far, can now be implemented with cur- rently available FPGAs. A tool-flow is presented, that au- tomatically generates the required homogeneous communi- cation infrastructure for any FPGA of the Xilinx Virtex-E to Virtex-5 family. Performance and area requirements are analyzed based on two typical example implementations of a Wishbone bus. |
Year | Venue | Keywords |
|---|---|---|
2007 | ERSA | data transfer |
DocType | Citations | PageRank |
Conference | 20 | 1.64 |
References | Authors | |
12 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jens Hagemeyer | 1 | 74 | 9.47 |
| Boris Kettelhoit | 2 | 45 | 5.97 |
| Markus Koester | 3 | 66 | 7.39 |
| Mario Porrmann | 4 | 420 | 50.91 |