Name
Title | ||
|---|---|---|
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits |
Abstract | ||
|---|---|---|
Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing ratio mismatch. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuits. The relationship between correlation and variation of capacitance ratio is also presented. Therefore, both mismatch and variation of capacitance ratio can be expressed in terms of capacitance correlation. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed up the time to market. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TCAD.2008.2006139 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
parallel unit capacitance,Capacitance Correlation,index terms—capacitance ratio,Analog Integrated Circuits,process variation,common centroid,analog integrated circuit,ratio mismatch,spatial correlation,device mismatch,capacitance correlation,Yield Enhancement,analog circuit,yield analysis.,similar parameter variation,accurate capacitance ratio,mismatch,capacitance ratio | Journal | 27 |
Issue | ISSN | Citations |
11 | 0278-0070 | 20 |
PageRank | References | Authors |
1.38 | 6 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pei-Wen Luo | 1 | 74 | 8.22 |
| Jwu-E Chen | 2 | 223 | 28.37 |
| Chin-Long Wey | 3 | 316 | 56.51 |
| Liang-Chia Cheng | 4 | 37 | 6.46 |
| Ji-Jan Chen | 5 | 116 | 9.34 |
| Wen-Ching Wu | 6 | 52 | 5.05 |