Name
Abstract | ||
|---|---|---|
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asynchronous. These types of cores provide native flow control that is compatible with this network, thus reducing adapter overhead and buffering needs by applying backpressure directly to the sending core. We show that under realistic traffic patterns our sample network meets performance requirements and uses less power compared to a similar design. This concept of a simplified network, along with latency insensitive cores lends itself well to meeting the needs of low-power interconnect components in future design processes. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/NOCS.2008.4492741 | NOCS |
Keywords | Field | DocType |
native flow control,latency insensitive core,latency insensitive network,performance requirement,future design process,adapter overhead,sample network,similar design,latency insensitive cores,soc core,network simplicity,buffering need,design process,protocols,circuits,low power electronics,throughput,bandwidth,network topology,network on a chip,logic design,system on chip,topology,flow control,network on chip | Asynchronous communication,Latency (engineering),Computer science,Network on a chip,Adapter (computing),Real-time computing,Network topology,Flow control (data),Throughput,Interconnection | Conference |
Citations | PageRank | References |
1 | 0.36 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Gebhardt | 1 | 13 | 1.63 |
| Junbok You | 2 | 47 | 3.79 |
| W. Scott Lee | 3 | 22 | 2.28 |
| Kenneth S. Stevens | 4 | 185 | 25.65 |