Name
Title | ||
|---|---|---|
A 4-10 Bit, 0.4-1 V Power Supply, Power Scalable Asynchronous Sar-Adc In 40 Nm-Cmos With Wide Supply Voltage Range Sar Controller |
Abstract | ||
|---|---|---|
This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flip-flop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1 V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and 1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1587/transfun.E96.A.443 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
analog-to-digital converter, successive approximation, asynchronous, differential flip-flop | Asynchronous communication,Control theory,Control theory,Voltage,CMOS,Electronic engineering,Analog-to-digital converter,Theoretical computer science,Successive approximation ADC,Mathematics,Switched-mode power supply,Scalability | Journal |
Volume | Issue | ISSN |
E96A | 2 | 0916-8508 |
Citations | PageRank | References |
2 | 0.46 | 2 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akira Shikata | 1 | 77 | 9.08 |
| Ryota Sekimoto | 2 | 77 | 9.08 |
| Kentaro Yoshioka | 3 | 54 | 9.04 |
| Tadahiro Kuroda | 4 | 659 | 213.23 |
| Hiroki Ishikuro | 5 | 285 | 52.15 |