Name
Abstract | ||
|---|---|---|
The demand for built-in self-repair (BISR) methodologies that improve the yield of embedded memories is growing. A typical BISR scheme requires circuit modules that perform built-in self-test (BIST), built-in redundancy analysis (BIRA), real-time address remapping, and so on. The objective of BISR design is to maximize the final yield while keeping a reasonably low hardware overhead. In this work, the authors propose cost and benefit models, and evaluate the economic effectiveness of typical memory BISR implementations. They also present a simulator for that purpose based on the proposed cost models. The results are useful for evaluating the BISR schemes and implementations. Experimental results show that memory size impacts the cost-effectiveness of BISR more than production volume does. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/MDT.2007.41 | IEEE Design & Test of Computers |
Keywords | DocType | Volume |
memory built-in self-repair,built-in redundancy analysis,bisr implementation,final yield,embedded memory,typical bisr scheme,built-in self-test,economic aspects,memory size,bisr scheme,bisr design,built-in self-repair,economics,algorithm design and analysis,economic model,product development,yield,mathematical model,cost effectiveness,overhead,economic models,profitability,redundancy,integrated circuit design,maintenance engineering,system on chip,design methodology,cost benefit analysis,costs and benefits,cmos integrated circuits,chip | Journal | 24 |
Issue | ISSN | Citations |
2 | 0740-7475 | 14 |
PageRank | References | Authors |
1.09 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rei-Fu Huang | 1 | 165 | 13.15 |
| Chao-Hsun Chen | 2 | 35 | 4.80 |
| Wu, Cheng-Wen | 3 | 1843 | 170.44 |