Name
Title | ||
|---|---|---|
Improving the testability and reliability of sequential circuits with invariant logic |
Abstract | ||
|---|---|---|
In this paper, we propose the use of logic implications to enhance online error detection capabilities and to improve the testing efficiency of an integrated circuit. These logic implications are implemented in hardware and help to verify that expected invariant circuit relationships are satisfied during field operation. Thus, any implication violation will indicate the presence of an error due to some faulty circuit behavior. In addition, checking these logic implications in hardware will create additional circuit outputs, which may be useful for compacting $n$-detect test sets. Our results show that logic implications can provide significant error detection and test pattern count reduction with very limited hardware overhead. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1785481.1785513 | ACM Great Lakes Symposium on VLSI |
Keywords | DocType | Citations |
online error detection capability,expected invariant circuit relationship,invariant logic,limited hardware overhead,sequential circuit,test pattern count reduction,additional circuit output,faulty circuit behavior,test set,significant error detection,logic implication,integrated circuit,error detection,sequential circuits,satisfiability | Conference | 1 |
PageRank | References | Authors |
0.35 | 12 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nuno Alves | 1 | 41 | 3.74 |
| Kundan Nepal | 2 | 41 | 5.88 |
| Jennifer Dworak | 3 | 1 | 0.35 |
| R. Iris Bahar | 4 | 878 | 84.31 |