Name
Abstract | ||
|---|---|---|
On-chip hardware coherence can scale gracefully as the number of cores increases. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2209249.2209269 | Commun. ACM |
Keywords | Field | DocType |
on-chip cache coherence,cores increase,on-chip hardware coherence,chip,cache coherence | Computer architecture,Cache invalidation,Cache pollution,Computer science,MESI protocol,Parallel computing,Cache algorithms,Theoretical computer science,Memory coherence,Cache coloring,Bus sniffing,Cache coherence | Journal |
Volume | Issue | ISSN |
55 | 7 | 0001-0782 |
Citations | PageRank | References |
126 | 3.04 | 13 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Milo M. K. Martin | 1 | 2677 | 125.22 |
| Mark D. Hill | 2 | 7371 | 582.90 |
| Daniel J. Sorin | 3 | 2213 | 125.31 |