Paper Info
Title
LDPC decoder with an adaptive wordwidth datapath for energy and BER co-optimization
Abstract
An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65nm CMOS. A 5.10mm2 low power decoder implementation achieves 85.7Gbps while operating at 185MHz and dissipates 16.4 pJ/bit at 1.3V with early termination. At 0.6V the decoder throughput is 9.3Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31mW. This is 4.6× lower than the state of the art reported power with an SNR loss of 0.35 dB at BER = 10-7.
Year
DOI
Venue
2013
10.1155/2013/913018
VLSI Design
Keywords
Field
DocType
low power mode,average power,decoder stay,post-layout power simulation,ber performance,ber requirement,decoder throughput,power consumption,ldpc decoder,ber co-optimization,low power decoder implementation,adaptive wordwidth datapath
Datapath,Efficient energy use,Computer science,Low-density parity-check code,Real-time computing,Electronic engineering,CMOS,Soft-decision decoder,Normal mode,Throughput,Power consumption
Journal
Volume
ISSN
Citations 
2013,
1065-514X
2
PageRank 
References 
Authors
0.40
20
3
Name
Order
Citations
PageRank
Tinoosh Mohsenin140647.43
Houshmand Shirani-mehr220.40
Bevan M. Baas329527.78