Name
Title | ||
|---|---|---|
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits |
Abstract | ||
|---|---|---|
Although clock skew can be utilized to reduce the clock period, the utilization of clock skew also limits the sharing of resources (including registers and functional units). Previous works have considered the influence of clock arrival times on register sharing, but they do not pay any attention to the influence of clock arrival times on functional unit sharing. As a result, extra functional units are often required during functional unit binding. Based on that observation, in this paper, we perform the simultaneous application of register binding and functional unit binding for the high-level synthesis of nonzero clock skew circuits. Our objective is to minimize the circuit area for working with the lower bound of the clock period. Compared with previous works, benchmark data show that our approach can achieve the lower bound of the clock period with a smaller area overhead. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ASPDAC.2012.6164953 | ASP-DAC |
Keywords | Field | DocType |
clock arrival times,circuit optimisation,minimum area overhead,clocks,clock period minimization,nonzero clock skew circuits,functional unit binding,minimisation,high-level synthesis,high level synthesis,adders,functional unit,synchronization,benchmark testing,lower bound,schedules,clock skew,clock synchronization,registers | Timing failure,Clock gating,Clock drift,Computer science,Clock domain crossing,Electronic engineering,Real-time computing,Clock skew,Digital clock manager,CPU multiplier,Clock angle problem | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4673-0770-3 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wen-Pin Tu | 1 | 21 | 4.32 |
| Shih-Hsu Huang | 2 | 203 | 38.89 |
| Chun-Hua Cheng | 3 | 59 | 12.00 |