Name
Abstract | ||
|---|---|---|
Today, at-speed test cost comprises a majority of the total test cost of a design. This derives from the fact that if the design has numerous data transfers between clock domains, we must generate test patterns for all of the synchronous data transfers to guarantee high reliability. Conventionally, at-speed test patterns are generated for each of the transfers separately. In order to reduce at-speed test application time, we take an approach to increase the number of the transfers tested concurrently. Evaluation results show that our approach is effective for that purpose. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ATS.2012.39 | Asian Test Symposium |
Keywords | Field | DocType |
at-speed test application time,evaluation result,multiple-timing clock waveforms,high reliability,at-speed test cost,numerous data transfer,synchronous data transfer,at-speed test pattern,clock domain,effective at-speed scan testing,test pattern,total test cost,automatic test pattern generation | Design for testing,Boundary scan,Automatic test pattern generation,Integration testing,Computer science,Automatic test equipment,Scan chain,Electronic engineering,Real-time computing,White-box testing,Test compression | Conference |
ISSN | ISBN | Citations |
1081-7735 E-ISBN : 978-0-7695-4876-0 | 978-0-7695-4876-0 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Iwata | 1 | 7 | 2.92 |
| Yoichi Maeda | 2 | 13 | 5.96 |
| Jun Matsushima | 3 | 13 | 4.09 |
| Masahiro Takakura | 4 | 5 | 3.18 |