Name
Abstract | ||
|---|---|---|
Excessive on-chip wire length and fast increasing fabrication costhave been the main factors impairing the effectiveness ofmonolithic System-on-Chip. This paper investigates a die stackingbased system integration strategy (2.5D system integration) toaddress these problems. The new scheme is design-tools-enabledrather than technology-driven. We developed a layout designframework, which is able to floorplan, place and route a VLSIdesign into stacked chips. Our results show that this new schemehas a potential to outperform its monolithic equivalent. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ICCD.2003.1240897 | ICCD |
Keywords | Field | DocType |
vlsi design,system on chip,system integration,physical design,chip,integrated circuit layout,vlsi,place and route | Integrated circuit layout,Computer science,Place and route,Circuit design,Electronic engineering,Standard cell,Physical design,Very-large-scale integration,System integration,Floorplan | Conference |
ISSN | ISBN | Citations |
1063-6404 | 0-7695-2025-1 | 8 |
PageRank | References | Authors |
0.66 | 9 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yangdong Deng | 1 | 429 | 44.78 |
| Wojciech Maly | 2 | 1976 | 352.57 |