Title
Combining optimizations in automated low power design
Abstract
Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs that meet speed and area constraints in the design space on Field-Programmable Gate Arrays (FPGAs). This combined approach enables trade-offs in power, speed and area: we show 63% reduction in power can be achieved with 27% increase in execution time. Compared to the sequential designs, our approach yields designs with up to 158 times reduction in execution time. Moreover, for a given execution time, our combined approach generates designs using up to 1.4 times less power than those produced by the same optimizations applied separately and can also find solutions missed by separating the optimizations.
Year
DOI
Venue
2010
10.1109/DATE.2010.5457104
DATE
Keywords
Field
DocType
power efficient designs,execution time,field-programmable gate arrays,design space,geometric programming,combining optimization,automated low power design,multilevel mapreduce,approach yields design,combined approach,sequential design,low-power electronics,combining optimizations,logic design,area constraint,sequential programs,field programmable gate arrays,times reduction,data reuse,electronic engineering computing,sequential program,power efficiency,memory management,field programmable gate array,constraint optimization,optimization,space exploration,concurrent computing,power generation,embedded system,speculation,low power electronics,dynamic scheduling,system on a chip,design optimization
Logic synthesis,Pipeline (computing),System on a chip,Computer science,Parallel computing,Real-time computing,Memory management,Concurrent computing,Dynamic priority scheduling,Constrained optimization,Low-power electronics
Conference
ISSN
ISBN
Citations 
1530-1591
978-1-4244-7054-9
16
PageRank 
References 
Authors
0.99
8
3
Name
Order
Citations
PageRank
Qiang Liu116016.34
Tim Todman26512.10
Wayne Luk33752438.09