Name
Abstract | ||
|---|---|---|
We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-/spl mu/m 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-/spl mu/m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/TVLSI.2005.853605 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
adders,high performance,cmos integrated circuits,0.35 micron,all-n transistor,ant,32 bit,power saving,dpanl adder,cmos technology,post-layout simulation,low-power design,logic design,low power design,dual-path all-n logic,dynamic logic circuit,dynamic-logic circuit,ant adder,lookahead adder,32-bit adder design,dual path all-n logic,reduced adder cell size,cmos,cmos chip,m cmos chip,circuit simulation,higher performance,chip,hardware,frequency,information security,embedded system,cryptography,dynamic logic,field programmable gate arrays | Logic synthesis,Logic gate,Adder,Computer science,Electronic engineering,Carry-lookahead adder,CMOS,Serial binary adder,Carry-save adder,Low-power electronics | Journal |
Volume | Issue | ISSN |
13 | 8 | 1063-8210 |
Citations | PageRank | References |
7 | 0.65 | 6 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ge Yang | 1 | 7 | 0.65 |
| Seong-ook Jung | 2 | 332 | 53.74 |
| Kwang-hyun Baek | 3 | 129 | 26.82 |
| Soo Hwan Kim | 4 | 16 | 8.11 |
| Suki Kim | 5 | 138 | 39.60 |
| Sung-Mo Steve Kang | 6 | 1198 | 213.14 |