Paper Info
Title
A Switch-Level Test Generation System.
Year
DOI
Venue
1992
10.1109/ICVD.1992.658019
VLSI Design
Keywords
Field
DocType
switch-level test generation system,sequential analysis,sequential circuits,system testing
Stuck-at fault,Clock signal,Automatic test pattern generation,Sequential logic,Computer science,Logic optimization,Real-time computing,Electronic engineering,Synchronous circuit,Fault Simulator,Asynchronous circuit
Conference
ISSN
ISBN
Citations 
1063-9667
0-8186-2465-5
2
PageRank 
References 
Authors
0.39
9
2
Name
Order
Citations
PageRank
Kent L. Einspahr1192.63
Sharad C. Seth267193.61