Paper Info
Title
Extending Modulo Scheduling with Memory Reference Merging
Abstract
We describe an extension of module scheduling, called "memory reference merging", which improves the management of cache bandwidth on microprocessors such as the DEC Alpha 21164. The principle is to schedule together memory references that are likely to be merged in a read buffer (LOADs), or a write buffer (STOREs). This technique has been used over several years on the Cray T3E block scheduler, and was later generalized to the Cray T3E software pipeliner. Experiments on the Gray T3E demonstrate the benefits of memory reference merging.
Year
DOI
Venue
1999
10.1007/b72146
CC
Field
DocType
Volume
Program optimization,Memory hierarchy,Scheduling (computing),Computer science,Cache,Modulo,Parallel computing,Write buffer,Memory organisation,DEC Alpha,Operating system
Conference
1575
ISSN
ISBN
Citations 
0302-9743
3-540-65717-7
0
PageRank 
References 
Authors
0.34
8
1
Name
Order
Citations
PageRank
Benoît Dupont de Dinechin119712.60