Name
Abstract | ||
|---|---|---|
Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TEST.2010.5699239 | ITC |
Keywords | Field | DocType |
integrated circuit testing,nanotechnology,integrated circuit yield loss,layout snippet clustering,systematic defect identification,diagnosis-implicated regions,layout snippets,lithographic hotspots,integrated circuit layout,nanoscaled technologies,clustering,feature extraction,integrated circuit,layout,design process,systematics,integrated circuits,clustering algorithms,chip,statistical significance | Integrated circuit layout,Computer science,Electronic engineering,Feature extraction,Chip,Snippet,Cluster analysis,Integrated circuit | Conference |
ISSN | ISBN | Citations |
1089-3539 | 978-1-4244-7206-2 | 18 |
PageRank | References | Authors |
0.90 | 27 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wing Chiu Tam | 1 | 109 | 7.29 |
| Osei Poku | 2 | 188 | 9.57 |
| Ronald D. Blanton | 3 | 253 | 26.57 |