Name
Abstract | ||
|---|---|---|
In flash memories, separate biasing of the source line and, in the case of a triple well process, of the well terminals of each sector, is required to prevent electrical stress of unselected sectors. This paper presents a hierarchical biasing architecture developed for this purpose. The lines carrying the voltages to be applied to the terminals of all the sectors in the same row are routed horizontally nearby the respective row. A vertical line controls the connection of the terminals of all sectors in the same column to the required bias lines. The proposed biasing organization allows silicon area saving thanks to simplified routing and reduced number of high voltage switches. The presented biasing architecture has been successfully used in a 64-Mbit 2-bit/cell NOR-type Flash memory and has been integrated in 0.18µm CMOS fabrication process. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/MTDT.2000.868612 | MTDT |
Keywords | Field | DocType |
respective row,separate biasing,64-mbit 2-bit,biasing architecture,required bias line,flash memories,hierarchical biasing architecture,hierarchical sector biasing organization,vertical line,source line,m cmos fabrication process,proposed biasing organization,stress,silicon,routing,voltage,switches,high voltage,decoding,nonvolatile memory | Flash memory,Source lines,Computer science,Voltage,Parallel computing,Cmos fabrication,Electronic engineering,High voltage,Charge trap flash,Memory architecture,Biasing | Conference |
ISSN | ISBN | Citations |
1087-4852 | 0-7695-0689-5 | 3 |
PageRank | References | Authors |
0.71 | 2 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rino Micheloni | 1 | 69 | 12.85 |
| Matteo Zammattio | 2 | 3 | 0.71 |
| Giovanni Campardo | 3 | 14 | 3.65 |
| Osama Khouri | 4 | 41 | 14.44 |
| Guido Torelli | 5 | 240 | 64.39 |