Paper Info
Title
Scan chain design for three-dimensional integrated circuits (3D ICs)
Abstract
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed to facilitate DFT (Design-For-Test). Recently, three-dimensional (3D) technologies have been proposed as a promising solution to continue technology scaling. In this paper, we study the scan chain construction for 3D ICs, examining the impact of 3D technologies on scan chain ordering. Three different 3D scan chain design approaches (namely, VIA3D, MAP3D, and OPT3D) are proposed and compared, with the experimental results for ISCAS89 benchmark circuits. The advantages as well as disadvantages for each approach are discussed. The results show that both MAP3D and VIA3D approaches require no changes of 2D scan chain algorithms, but OPT3D can achieve the best wire length reduction for the scan chain design. The average scan chain wire length of six ISCAS89 benchmarks obtained from OPT3D has 46.0% reduction compared to the 2D scan chain design. To the best of our knowledge, this is the first study on scan chain design for 3D integrated circuits.
Year
DOI
Venue
2007
10.1109/ICCD.2007.4601902
ICCD
Keywords
Field
DocType
opt3d,integrated circuit testing,wire length reduction,via3d,iscas89 benchmark circuits,three-dimensional integrated circuits,ic designs,scan chain design,integrated circuit design,map3d,design for testability,design-for-test,integrated circuit,design for test,three dimensional
Design for testing,Testability,Technology scaling,Computer science,Parallel computing,Scan chain,Electronic engineering,Integrated circuit design,Electronic circuit,Computer hardware,Integrated circuit
Conference
ISSN
ISBN
Citations 
1063-6404 E-ISBN : 978-1-4244-1258-7
978-1-4244-1258-7
30
PageRank 
References 
Authors
2.16
14
3
Name
Order
Citations
PageRank
Xiaoxia Wu153538.61
Paul Falkenstern2845.25
Yuan Xie36430407.00