Paper Info
Title
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores
Abstract
3D integration is a promising new technology for tightly integrating multiple active silicon layers into a single chip stack. Both the integration of heterogeneous tiers and the partitioning of functional units across tiers leads to significant improvements in functionality, area, performance, and power consumption. Managing the complexity of 3D design is a significant challenge that will require a system-on-chip approach, but the application of SOC design to 3D necessitates extensions to current test methodology. In this paper, we propose extending test wrappers, a popular SOC DFT technique, into the third dimension. We develop an algorithm employing the Best Fit Decreasing and Kernighan-Lin Partitioning heuristics to produce 3D wrappers that minimize test time, maximize reuse of routing resources across test modes, and allow for different TAM bus widths in different test modes. On average the two variants of our algorithm reuse 93% and 92% of the test wrapper wires while delivering test times of just 0.06% and 0.32% above the minimum.
Year
DOI
Venue
2011
10.1109/ICCD.2011.6081381
ICCD
Keywords
Field
DocType
test wrapper,test mode,different tam bus width,post-bond test,popular soc dft technique,current test methodology,test time,test wrapper wire,embedded core,different test mode,algorithm reuse,soc design,design for testability,algorithm design and analysis,integrated circuit packaging,integrated circuit design,silicon,network routing,system on chip,system on a chip
Design for testing,Test method,System on a chip,Algorithm design,Reuse,Computer science,Real-time computing,Chip,Integrated circuit design,Heuristics,Embedded system
Conference
Citations 
PageRank 
References 
2
0.40
15
Authors
5
Name
Order
Citations
PageRank
Dean L. Lewis131215.89
Shreepad Panth221215.43
Xin Zhao322014.14
Sung Kyu Lim41688168.71
Hsien-Hsin Sean Lee51657102.66