Paper Info
Title
Efficient performance estimation with very small sample size via physical subspace projection and maximum a posteriori estimation
Abstract
In this paper, we propose a novel integrated circuits performance estimation algorithm through a physical subspace projection and maximum-a-posteriori (MAP) estimation. Our goal is to estimate the distribution of a target circuit performance with very small measurement sample size from on-chip monitor circuits. The key idea in this work is to exploit the fact that simulation and measurement data are physically correlated under different circuit configurations and topologies. First, different groups of measurements are projected to a subspace spanned by a set of physical variables. The projection is achieved by performing a sensitivity analysis of measurement parameters with respect to the subspace variables using a virtual source MOSFET compact model. Then a Bayesian treatment is developed by introducing prior distributions over these subspace variables. Maximum a posteriori estimation is then applied using the prior, and an expectation-maximization (EM) algorithm is used to estimate the circuit performance. The proposed method is validated by post-silicon measurement for a commercial 28-nm process. An average error reduction of 2x is achieved which can be translated to 32x reduction on data size needed for samples on the same die. A 150x and 70x sample size reduction on training dies is also achieved compared to traditional least-square fitting method and least-angle regression method, respectively, without reducing accuracy.
Year
DOI
Venue
2014
10.7873/DATE.2014.239
DATE
Keywords
DocType
ISSN
efficient performance estimation,estimation algorithm,different circuit configuration,semiconductor device models,measurement parameters,expectation-maximisation algorithm,small sample size,performance estimation,expectation-maximization algorithm,virtual source mosfet compact model,integrated circuits,subspace variables,size 28 nm,maximum a posteriori estimation,physical subspace projection,average error reduction,subspace variable,on-chip monitor circuits,measurement parameter,postsilicon measurement,bayes methods,very small sample size,small measurement sample size,commercial process,measurement data,post-silicon measurement,circuit performance,posteriori estimation,bayesian treatment,map estimation,sensitivity analysis,em algorithm,mosfet,expectation maximization algorithm,system on chip,estimation,semiconductor device modeling
Conference
1530-1591
Citations 
PageRank 
References 
5
0.48
7
Authors
6
Name
Order
Citations
PageRank
Li Yu1191.90
Sharad Saxena25813.84
Christopher Hess3141.68
Ibrahim M. Elfadel424244.16
Dimitri A. Antoniadis521739.43
Duane Boning620149.37