Name
Abstract | ||
|---|---|---|
This work describes the carry-compact addition (CCA), a novel addition scheme that allows the acceleration of carry-chain computations on contemporary FPGA devices. While based on concepts known from the carry-look ahead addition and from parallel prefix adders, their adaptation by the CCA takes the context of an FPGA as implementation environment into account. These typically provide carry-chain structures to accelerate the simple ripple-carry addition (RCA). Rather than contrasting this scheme with the hierarchical addition approaches favored in hard-core VLSI designs, the CCA combines the benefits of both and uses hierarchical structures to shorten the critical path, which is still left on a core carry chain. In contrast to previous studies examining the asymptotically superior parallel prefix adders on FPGAs, the CCA is shown to outperform the standard RCA already for operand widths starting at 50~bits. Wider adders such as used in extended-precision floating-point units and in cryptographic applications even benefit from increasing speedups. The concrete mapping of the CCA as achieved for current Xilinx and Altera architectures is described and shown to be very favorable so as to yield a high speedup for a very modest investment of additional LUT resources. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ARITH.2011.22 | IEEE Symposium on Computer Arithmetic |
Keywords | Field | DocType |
carry-chain computation,accelerating computations,operand compaction,fpga carry chains,carry-compact addition,hierarchical structure,asymptotically superior parallel prefix,simple ripple-carry addition,contemporary fpga device,novel addition scheme,carry-chain structure,parallel prefix adder,hierarchical addition,floating point arithmetic,cryptography,vlsi,fpga,vlsi design,lut,addition,critical path,field programmable gate arrays,adders,acceleration,compaction,floating point unit | Lookup table,Adder,Computer science,Floating point,Parallel computing,Operand,Field-programmable gate array,Critical path method,Very-large-scale integration,Speedup | Conference |
ISSN | Citations | PageRank |
1063-6889 | 0 | 0.34 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas B. Preuβer | 1 | 3 | 0.85 |
| Martin Zabel | 2 | 52 | 5.27 |
| Rainer G. Spallek | 3 | 137 | 25.30 |