Name
Title | ||
|---|---|---|
A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1 |
Abstract | ||
|---|---|---|
This paper presents a power-efficient, high-linearity pipelined ADC, utilizing a combined front-end of the sample/hold circuit (S/H) and the first multiplying digital-to-analog converter (MDAC1). In contrast with the conventional merged sample-and-hold amplifier (SHA) and first MDAC, the front-end uses an opamp split-sharing scheme to meet the different gain and bandwidth requirements of both the S/H and the first MDAC. This opamp split-sharing scheme mitigates the memory effect without a dedicated clock phase and avoids crosstalk. In the back-end ADC, 4.5-bit opamp-sharing MDACs with four-input operational trans-conductance amplifiers (OTAs) are used for further power saving. Implemented in a 0.18-μm CMOS process, the 14-bit ADC achieves a spurious-free dynamic range (SFDR) of 89.1 dB and a signal-to-noise plus distortion ratio (SNDR) of 70.2 dB, with a sampling rate of 100 MS/s and an input of 15.5 MHz. For input signals up to 220 MHz, measured SFDR and SNDR are maintained above 82.7 dB and 66.2 dB, respectively. The ADC consumes 92 mW with a 1.8-V supply, occupying an area of 6.3 mm2. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TCSI.2013.2252643 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
clock phase,cmos process,memory effect,cmos integrated circuits,back-end adc,ota,wideband,cmos,combined front-end,analogue-digital conversion,operational transconductance amplifiers,operational amplifiers,sha,word length 14 bit,opamp-sharing,voltage 1.8 v,pipeline,sfdr,clocks,size 0.18 mum,sample-and-hold amplifier,spurious-free dynamic range,analog-to-digital converter (adc),frequency 15.5 mhz,low power,first multiplying digital-to-analog converter,s-h circuit,mdac1,sub-sampling,power 92 mw,power-efficient pipelined adc,opamp split-sharing,word length 4.5 bit,sample and hold circuits,high-linearity pipelined adc,digital-analogue conversion,sample-hold circuit | Sampling (signal processing),Linearity,CMOS,Spurious-free dynamic range,Electronic engineering,Bandwidth (signal processing),Successive approximation ADC,Electrical engineering,Mathematics,Operational amplifier,Amplifier | Journal |
Volume | Issue | ISSN |
60 | 11 | 1549-8328 |
Citations | PageRank | References |
6 | 0.47 | 13 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhenyu Wang | 1 | 41 | 29.53 |
| Mingshuo Wang | 2 | 13 | 3.24 |
| Weiru Gu | 3 | 7 | 1.19 |
| Chixiao Chen | 4 | 13 | 5.20 |
| Fan Ye | 5 | 63 | 21.55 |
| Junyan Ren | 6 | 154 | 41.40 |