| A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS | 1 | 0.36 | 2021 |
| A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Power Technique | 0 | 0.34 | 2021 |
| Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization | 0 | 0.34 | 2021 |
| A Hardware-Efficient Calibrator for SAR-Pipelined ADCs with a Layer-based Sharing Neural Network | 0 | 0.34 | 2021 |
| A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio | 0 | 0.34 | 2021 |
| A Partially Binarized And Fixed Neural Network Based Calibrator For Sar-Pipelined Adcs Achieving 95.0-Db Sfdr | 0 | 0.34 | 2021 |
| A 12-bit SAR ADC Using Pseudo-Dynamic Weighting C-DAC for Capacitor Error Calibration. | 0 | 0.34 | 2020 |
| A Fast Response Reference Voltage Buffer for 12b 200MS/s SAR ADC | 0 | 0.34 | 2020 |
| A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET | 0 | 0.34 | 2020 |
| A 10-18 GHz GaN Power Amplifier Based on Asymmetric Magnetically Coupled Resonator. | 0 | 0.34 | 2020 |
| A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications | 0 | 0.34 | 2019 |
| A 140 GHz, 4 dB Noise-Figure Low-Noise Amplifier Design with the Compensation of Parasitic Capacitance C<inf>GS</inf> | 1 | 0.43 | 2019 |
| A Band-Pass Noise-Shaping Modulator Using the Error-Feedback Structure on a 10-bit SAR ADC | 0 | 0.34 | 2019 |
| A 256mhz Analog Baseband Chain With Tunable Bandwidth And Gain For Uwb Receivers | 0 | 0.34 | 2019 |
| A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier. | 2 | 0.41 | 2018 |
| A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier | 0 | 0.34 | 2017 |
| Transformer-based varactor-less 96GHz–110GHz VCO and 89GHz–101GHz QVCO in 65nm CMOS | 1 | 0.35 | 2016 |
| A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network | 0 | 0.34 | 2016 |
| I/Q Imbalance Estimation In Ofdm Systems | 0 | 0.34 | 2015 |
| Greedy approach based heuristics for partitioning SpMxV on FPGAs | 0 | 0.34 | 2015 |
| A High Power-Efficient Lvds Output Driver With Adjustable Feed-Forward Capacitor Compensation | 2 | 0.48 | 2015 |
| A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system | 0 | 0.34 | 2015 |
| 100ms/S 9-Bit 0.43mw Sar Adc With Custom Capacitor Array | 0 | 0.34 | 2015 |
| An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators | 0 | 0.34 | 2015 |
| A Monolithic Sub-Sampling Pll Based 6-18 Ghz Frequency Synthesizer For C, X, Ku Band Communication | 0 | 0.34 | 2015 |
| Greedy Approach Based Heuristics For Partitioning Sparse Matrices | 0 | 0.34 | 2015 |
| A 100MS/s 5bit fully digital flash ADC with standard cells | 0 | 0.34 | 2015 |
| Switch-Back Based On Charge Equalization Switching Technique For Sar Adc | 0 | 0.34 | 2015 |
| General expression based inner loop unrolling scheme for TV-GD algorithm adopted in photoacoustic imaging | 0 | 0.34 | 2014 |
| A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding. | 0 | 0.34 | 2014 |
| A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier | 2 | 0.51 | 2014 |
| No zero padded sparse matrix-vector multiplication on FPGAs | 0 | 0.34 | 2014 |
| Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer | 10 | 0.80 | 2014 |
| A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators | 0 | 0.34 | 2014 |
| An overview of new design techniques for high performance CMOS millimeter-wave circuits | 1 | 0.41 | 2014 |
| A 42fj 8-Bit 1.0-Gs/S Folding And Interpolating Adc With 1ghz Signal Bandwidth | 0 | 0.34 | 2014 |
| A 0.13-µm CMOS 0.1-12GHz active balun-LNA for multi-standard applications. | 0 | 0.34 | 2013 |
| A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1 | 6 | 0.47 | 2013 |
| A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line | 2 | 0.42 | 2013 |
| A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system | 0 | 0.34 | 2013 |
| Automatic gain control algorithm with high-speed and double closed-loop in UWB system | 1 | 0.37 | 2013 |
| Power efficient SAR ADC with optimized settling technique | 1 | 0.39 | 2013 |
| A 96-GHz Oscillator by High-Q Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS. | 3 | 0.59 | 2013 |
| Low-complexity synchronizer used in DC-OFDM UWB system | 0 | 0.34 | 2013 |
| A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers | 0 | 0.34 | 2013 |
| Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers | 3 | 0.55 | 2013 |
| A DLL based low-phase-noise clock multiplier with offset-tolerant PFD | 0 | 0.34 | 2013 |
| Carrier Frequency Offset and I/Q Imbalance Compensation for MB-OFDM Based UWB System | 0 | 0.34 | 2013 |
| A Mixed Sample-Time Error Calibration Technique In Time-Interleaved Adcs | 3 | 0.52 | 2013 |
| A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC | 0 | 0.34 | 2013 |
