Name
Abstract | ||
|---|---|---|
A novel method is proposed in order to calculate the probability of an SET resulting into SEU. The method is proposed to calculate the propagation of SET to the output gate at any time instant within the latching window. The method uses symbolic simulation and disjoint covers of appropriately formulated functions to take into consideration re-convergent paths and therefore more accurate calculations. This is evaluated experimentally on the benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/IOLTS.2010.5560234 | On-Line Testing Symposium |
Keywords | Field | DocType |
output gate,novel method,symbolic simulation,accurate calculation,probabilistic method,benchmark circuit,combinational logic,time instant,consideration re-convergent path,data structures,boolean functions,combinational circuits,logic gates,probability | Boolean function,Symbolic simulation,Data structure,Logic gate,Disjoint sets,Computer science,Algorithm,Combinational logic,Probabilistic method,Electronic engineering,Single event upset | Conference |
ISBN | Citations | PageRank |
978-1-4244-7724-1 | 4 | 0.45 |
References | Authors | |
10 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sreenivas Gangadhar | 1 | 18 | 3.50 |
| Spyros Tragoudas | 2 | 625 | 88.87 |