Paper Info
Title
On-Chip Calibration Technique For Delay Line Based Bist Jitter Measurement
Abstract
This paper describes an on-chip calibration technique for delay line based Time-to-Digital Converters (TDC) used in jitter measurement Built-in Self-Test (BIST). The proposed technique utilizes Pulse Width Modulation (PWM) to generate accurate voltages to control delay elements within the TDC. Calibration is performed in three stages; accuracy fine-tuning, measurement dynamic range adjustment, and characteristic curve generation. Preliminary simulation results using the calibration technique on a modified Vernier Delay Line (VDL) BIST provided a cycle-to-cycle jitter resolution of similar to5 ps. The calibration design consists of digital CMOS 2 components and has a potential die area of 0.03 mum(2). Calibration time is less than 1.1ms and only a single external calibration input pin is required in addition to the existing BIST.
Year
DOI
Venue
2004
10.1109/ISCAS.2004.1328352
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS
Keywords
Field
DocType
jitter,dynamic range,chip,pulse width modulation,calibration
Dynamic range,Control theory,Computer science,Vernier scale,Voltage,Pulse-width modulation,Electronic engineering,CMOS,Jitter,Calibration,Built-in self-test
Conference
Citations 
PageRank 
References 
4
0.60
4
Authors
2
Name
Order
Citations
PageRank
Bryan Nelson1192.19
Mani Soma249773.41