Name
Abstract | ||
|---|---|---|
Flowmap ([1]) was the first delay-optimal algorithm for the technology mapping of LUT-based FPGAs. However, even though this algorithm is polynomial, rapid prototyping using FPGAs requires faster solutions. This paper provides an efficient parallelization of flowmap that minimizes locking on shared memory architectures. The influence of scheduling strategies and technology-specific parameters on speedups is studied. The expected running time is also analyzed. The parallel algorithms yield speedups of around 4 to 5 on 8 processors. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1007/3-540-61626-8_109 | Euro-Par, Vol. I |
Keywords | Field | DocType |
technology mapping,lut-based fpgas,parallel algorithm,shared memory | Rapid prototyping,Lookup table,Polynomial,Shared memory,Scheduling (computing),Parallel algorithm,Computer science,Parallel computing,Field-programmable gate array,Technology mapping,Distributed computing | Conference |
ISBN | Citations | PageRank |
3-540-61626-8 | 2 | 0.45 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vamsi Boppana | 1 | 267 | 20.98 |
| Prashant Saxena | 2 | 210 | 25.24 |
| Prithviraj Banerjee | 3 | 2763 | 337.99 |
| W. Kent Fuchs | 4 | 1469 | 279.02 |
| C. L. Liu | 5 | 6191 | 970.79 |