Name
Title | ||
|---|---|---|
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture |
Abstract | ||
|---|---|---|
In this paper we present a novel function-based test generation technique for path delay faults (PDFs) under the launch-off-capture (LOC) scan architecture. The LOC architecture imposes the condition that the second test pattern must be a functional response of the initial scan test pattern. The proposed function-based LOC methodology incorporates traditional function-based ATPG techniques alongside an implicit framework to efficiently identify testable PDFs under the LOC scan architecture, and avoids the complex backtracking performed by structural techniques which may abort PDF classifications for path intensive designs. The effectiveness and scalability of the proposed method is demonstrated on the path intensive ISCAS 89 benchmarks. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VLSID.2007.86 | VLSI Design |
Keywords | Field | DocType |
novel function-based test generation,path intensive design,path delay,testable pdfs,path delay fault,intensive iscas,proposed function-based loc methodology,test pattern,function-based atpg,traditional function-based atpg technique,launch-off-capture scan architecture,loc architecture,automatic test pattern generation,functional response | Boundary scan,Automatic test pattern generation,Architecture,Computer science,Path delay,Scan chain,Electronic engineering,Real-time computing,Backtracking,Test compression,Scalability | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-7695-2762-0 | 4 |
PageRank | References | Authors |
0.44 | 12 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Edward Flanigan | 1 | 14 | 3.05 |
| Rajsekhar Adapa | 2 | 35 | 3.92 |
| Hailong Cui | 3 | 15 | 1.76 |
| Michael Laisne | 4 | 9 | 1.20 |
| Spyros Tragoudas | 5 | 625 | 88.87 |
| Tsvetomir Petrov | 6 | 11 | 1.32 |