Paper Info
Title
Improved throughput bit-serial multiplier for GF(2m) fields
Abstract
High throughput is a crucial factor in bit-serial GF(2^m) fields multiplication for a variety of different applications including cryptography, error coding detection and computer algebra. The throughput of a multiplier is dependent on the required number of clock cycles to reach a result and its critical path delay. However, most bit-serial GF(2^m) multipliers do not manage to reduce the required number of clock cycles below the threshold of m clock cycles without increasing dramatically their critical path delay. This increase is more evident if a multiplier is designed to be versatile. In this article, a new versatile bit-serial MSB multiplier for GF(2^m) fields is proposed that achieves a 50% increase on average in throughput when compared to other designs, with a very small increase in its critical path delay. This is achieved by an average 33.4% reduction in the required number of clock cycles below m. The proposed design can handle arbitrary bit-lengths upper bounded by m and is suitable for applications where the field order may vary.
Year
DOI
Venue
2009
10.1016/j.vlsi.2008.07.003
Integration
Keywords
Field
DocType
small increase,high throughput,bit-serial gf,m clock cycle,critical path delay,fields multiplication,required number,improved throughput bit-serial multiplier,arbitrary bit-lengths,proposed design,clock cycle,hardware,multiplication,critical path,computer algebra,upper bound,galois field,cryptography,galois fields
Finite field,Computer science,Upper and lower bounds,Circuit design,Error detection and correction,Electronic engineering,Multiplier (economics),Multiplication,Critical path method,Throughput
Journal
Volume
Issue
ISSN
42
2
Integration, the VLSI Journal
Citations 
PageRank 
References 
10
0.62
19
Authors
4
Name
Order
Citations
PageRank
G. Selimis1314.40
Apostolos P. Fournaris211419.56
harris e michail315618.29
Odysseas Koufopavlou48915.92