| Design and validation of an agent-based driving simulator. | 0 | 0.34 | 2018 |
| Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures. | 2 | 0.37 | 2016 |
| Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs. | 3 | 0.41 | 2016 |
| Pipelined SHA-3 Implementations on FPGA: Architecture and Performance Analysis | 4 | 0.54 | 2015 |
| Hardware implementation of the Totally Self-Checking SHA-256 hash core | 2 | 0.38 | 2015 |
| High performance pipelined FPGA implementation of the SHA-3 hash algorithm | 4 | 0.43 | 2015 |
| Optimising the SHA-512 cryptographic hash function on FPGAs | 4 | 0.53 | 2014 |
| On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs. | 2 | 0.37 | 2014 |
| Distribution Of Cultural Content Through Exploitation Of Cryptographic Algorithms And Hardware Identification | 0 | 0.34 | 2014 |
| A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families. | 1 | 0.35 | 2013 |
| High-performance FPGA implementations of the cryptographic hash function JH. | 1 | 0.36 | 2013 |
| Evolution of the e-museum concept through exploitation of cryptographic algorithms | 2 | 0.63 | 2012 |
| A data locality methodology for matrix–matrix multiplication algorithm | 6 | 0.45 | 2012 |
| On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function. | 1 | 0.39 | 2012 |
| An Intelligent Transportation System for Accident Risk Index Quantification. | 0 | 0.34 | 2012 |
| On the exploitation of a high-throughput SHA-256 FPGA design for HMAC | 5 | 0.49 | 2012 |
| High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach. | 0 | 0.34 | 2012 |
| Cipher Block Based Authentication Module: a Hardware Design Perspective | 2 | 0.40 | 2011 |
| A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization | 8 | 0.54 | 2011 |
| A robotic system for home security enhancement | 3 | 0.43 | 2010 |
| Ultra High Speed SHA-256 Hashing Cryptographic Module for IPSec Hardware/Software Codesign. | 2 | 0.42 | 2010 |
| Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor. | 0 | 0.34 | 2010 |
| A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores | 13 | 0.82 | 2009 |
| Improved throughput bit-serial multiplier for GF(2m) fields | 10 | 0.62 | 2009 |
| An RNS implementation of an Fpelliptic curve point multiplier | 7 | 0.52 | 2009 |
| An RNS Implementation of an <formula formulatype="inline"> <tex Notation="TeX">$F_{p}$</tex></formula> Elliptic Curve Point Multiplier | 33 | 1.24 | 2009 |
| Assessing Students' Learning in MIS Using Concept Mapping. | 0 | 0.34 | 2009 |
| An RNS Implementation of an Fp Elliptic Curve Point Multiplier. | 0 | 0.34 | 2009 |
| Novel Hardware Implementation of the Cipher Message Authentication Code | 0 | 0.34 | 2008 |
| Server side hashing core exceeding 3 Gbps of throughput | 6 | 0.43 | 2007 |
| Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core | 0 | 0.34 | 2006 |
| VLSI design and implementation of reconfigurable cryptographic systems for symmetric encryption. | 0 | 0.34 | 2005 |
| Optimizing SHA-1 hash function for high throughput with a partial unrolling study | 6 | 0.91 | 2005 |
| Novel high throughput implementation of SHA-256 hash function through pre-computation technique. | 3 | 0.47 | 2005 |
| A low-power and high-throughput implementation of the SHA-1 hash function | 16 | 1.70 | 2005 |
| Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function. | 10 | 0.73 | 2004 |
