Name
Abstract | ||
|---|---|---|
This paper presents a universal BCH encoder and decoder that can support multiple error-correction capabilities. A novel encoding architecture and on-demand syndrome calculation technique is proposed to reduce both hardware complexity and power consumption. Based on the proposed methods, 32-parallel universal encoder and decoder are designed for BCH (8192+14t, 8192, t) codes, where the error-correction capability t is configurable to 8, 11, 16, 24, 32, and 64. The prototype chip achieves a throughput of 7.3 Gb/s and occupies 2.24 mm2 in 0.13μm CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ASPDAC.2014.6742862 | ASP-DAC |
Keywords | Field | DocType |
solid-state drives,ssd controllers,hardware complexity reduction,bch codes,universal bch encoder,multiple error-correction capabilities,cmos technology,bit rate 7.3 gbit/s,cmos digital integrated circuits,universal bch decoder,on-demand syndrome calculation technique,size 0.13 mum,encoding architecture,error correction,flash memories,power consumption reduction | Computer science,Real-time computing,Electronic engineering,Chip,Error detection and correction,CMOS,BCH code,Encoder,Throughput,Encoding (memory),Power consumption | Conference |
ISSN | Citations | PageRank |
2153-6961 | 4 | 0.56 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hoyoung Yoo | 1 | 75 | 9.99 |
| Youngjoo Lee | 2 | 74 | 18.85 |
| In-Cheol Park | 3 | 888 | 124.36 |