Name
Abstract | ||
|---|---|---|
Path delay testing is becoming increasingly important for high-performance chip testing in the presence of process variation. To guarantee full process space coverage, the ensemble of critical paths of all chips irrespective of their manufacturing process conditions needs to be tested, as different chips may have different critical paths. Existing coverage-based path selection techniques, however, suffer from the loss of coverage after ATPG (automatic test pattern generation), i.e., although the pre-ATPG path selection achieves good coverage, after ATPG, the coverage can be severely reduced as many paths turn out to be unsensitizable. This paper presents a novel path selection algorithm that, without running ATPG, selects a set of n paths to achieve near optimal post-ATPG coverage. Details of the algorithm and its optimality conditions are discussed. Experimental results show that, compared to the state-of-the-art, the proposed algorithm achieves not only superior post-ATPG coverage, but also significant runtime speedup. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1687399.1687419 | ICCAD |
Keywords | Field | DocType |
n path,different critical path,good coverage,coverage-based path selection technique,pre-atpg path selection,path delay testing,optimal post-atpg coverage,novel path selection algorithm,critical path,near optimal post-atpg process,superior post-atpg coverage,full process space coverage,algorithm design and analysis,automatic test pattern generation,process variation,total quality management,chip | Automatic test pattern generation,Algorithm design,Fault coverage,Computer science,Selection algorithm,Chip,Real-time computing,Process variation,Basis path testing,Speedup | Conference |
Citations | PageRank | References |
6 | 0.49 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiong Jinjun | 1 | 801 | 86.79 |
| Yiyu Shi | 2 | 553 | 83.22 |
| Vladimir Zolotov | 3 | 1367 | 109.07 |
| Chandu Visweswariah | 4 | 615 | 60.90 |