Paper Info
Title
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture
Abstract
This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses a boosted and offset-grounded data storage (BOGS) scheme. The key target of BOGS is to minimize the charge amount supplied from the embedded charge pump circuits, which are required to boost the effective gate to source voltage (V/sub 0/=V/sub GS/-V/sub T/) up to 0.8 V necessary to achieve 100 MHz operation even at 0.5 V single power supply. Thus, the key low-power strategy of BOGS is "putting the right (higher efficiency) boosted power-supply from charge pump circuit into the right position (less power consumed transistor) in a SRAM cell." This paper is focused on why BOGS can realize a greater savings of the charge amount supplied from the boosted power-line and can reduce the power dissipation to /spl les/1/30.4 and /spl les/1/3.9 compared to the previously reported negative source-line drive (NSD) scheme and negative word-line drive (NWD) scheme, respectively, while achieving a 0.5 V/100 MHz operation.
Year
DOI
Venue
1997
10.1109/92.645064
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
offset-grounded data storage,power dissipation,sram cell,v single power supply,embedded charge pump circuit,1-mbit sram cell architecture,sub gs,key low-power strategy,mhz operation,charge amount,charge pump circuit,cmos technology,data storage,central processing unit,threshold voltage,circuits,charge pump
Computer science,Voltage source,Circuit design,CMOS,Electronic engineering,Charge pump,Electronic circuit,Transistor,Threshold voltage,Electrical engineering,Memory architecture
Journal
Volume
Issue
ISSN
5
4
1063-8210
Citations 
PageRank 
References 
5
2.17
1
Authors
4
Name
Order
Citations
PageRank
Hiroyuki Yamauchi118030.79
Toru Iwata2104.78
Hironori Akamatsu36711.37
Akira Matsuzawa446588.10