A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses | 33 | 1.95 | 2008 |
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. | 29 | 6.58 | 2007 |
A Stable Sram Mitigating Cell-Margin Asymmetricity With A Disturb-Free Biasing Scheme | 0 | 0.34 | 2007 |
0.3-1.5v Embedded Sram Core With Write-Replica Circuit Using Asymmetrical Memory Cell And Source-Level-Adjusted Direct-Sense-Amplifier | 0 | 0.34 | 2005 |
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture | 5 | 2.17 | 1997 |