Name
Abstract | ||
|---|---|---|
Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ATS.2011.97 | Asian Test Symposium |
Keywords | Field | DocType |
low-power srams,power gating,memory block,defective power,power consumption,power supply,sram core-cells,test solutions,embed power,detailed analysis,failure analysis,memory cell,supply voltage,logic gates,logic gate,sram | Logic gate,Computer science,Voltage,Electronic engineering,Static random-access memory,Real-time computing,Power demand,Power gating,Power consumption | Conference |
ISSN | Citations | PageRank |
1081-7735 | 1 | 0.38 |
References | Authors | |
2 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| L. B. Zordan | 1 | 5 | 1.86 |
| A. Bosio | 2 | 113 | 15.51 |
| L. Dilillo | 3 | 44 | 9.49 |
| P. Girard | 4 | 478 | 41.91 |
| S. Pravossoudovitch | 5 | 689 | 54.12 |
| A. Todri | 6 | 7 | 3.85 |
| A. Virazel | 7 | 169 | 23.25 |
| N. Badereddine | 8 | 18 | 2.98 |