Paper Info
Title
Power-Aware Test Generation With Guaranteed Launch Safety For At-Speed Scan Testing
Abstract
At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by excessive launch switching activity (LSA) caused by test stimulus launching in the at-speed test cycle. However, previous low-power test generation techniques can only reduce LSA to some extent but cannot guarantee launch safety. This paper proposes a novel & practical power-aware test generation flow, featuring guaranteed launch safety. The basic idea is to enhance ATPG with a unique two-phase (rescue & mask) scheme by targeting at the real cause of the launch safety problem, i.e., the excessive LSA in the neighboring areas (namely impact areas) around long paths sensitized by a test vector. The rescue phase is to reduce excessive LSA in impact areas in a focused manner, and the mask phase is to exclude from use in fault detection the uncertain test response at the endpoint of any long sensitized path that still has excessive LSA in its impact area even after the rescue phase is executed. This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.
Year
DOI
Venue
2011
10.1109/VTS.2011.5783778
2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS)
Keywords
Field
DocType
test generation, test power, at-speed scan testing, power supply noise, launch safety
Test vector,Automatic test pattern generation,Computer science,Logic testing,Fault detection and isolation,Test quality,Real-time computing,Electronic engineering,Reliability engineering,Test power
Conference
ISSN
Citations 
PageRank 
1093-0167
15
0.65
References 
Authors
15
8
Name
Order
Citations
PageRank
Xiaoqing Wen179077.12
Kazunari Enokimoto2191.75
Kohei Miyase356238.71
Yuta Yamato41389.45
Michael A. Kochte527627.23
Seiji Kajihara698973.60
Patrick Girard777689.03
Mohammad Tehranipoor83181243.40