Name
Abstract | ||
|---|---|---|
This paper describes an architecture and FPGA synthesis tool chain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is amenable to automatic, semi-automatic, or even manual parallelization. Whereas accelerator approaches have traditionally achieved energy benefits as a side effect from increasing performance via parallel execution, ICERs aim to achieve energy gains even on code with little exploitable parallelism. Traditional approaches to automatically generating accelerators from existing software rely on inferring parallel execution from serial code, so they face the same code analysis challenges as parallelizing compilers. In contrast, because the ICER approach targets energy rather than performance, it easily scales to large, irregular applications that are poor candidates for traditional acceleration. Our results show that, compared to a baseline system with soft processor cores, ICERs can reduce energy consumption by up to 9.5x for the code they target and 2.8x for whole applications. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/FCCM.2011.45 | Field-Programmable Custom Computing Machines |
Keywords | Field | DocType |
traditional approach,energy cost,energy gain,irregular code bases,traditional acceleration,energy consumption,icer approach targets energy,parallel execution,code analysis challenge,large software system,serial code,soft processor systems,energy benefit,energy efficiency,hardware accelerator,energy efficient,hardware,coprocessors,viterbi algorithm,field programmable gate arrays,code analysis,high level synthesis,field programmable gate array,acceleration,benchmark testing,computer architecture | Static program analysis,Efficient energy use,Computer science,High-level synthesis,Parallel computing,Compiler,Real-time computing,Coprocessor,Energy consumption,Multi-core processor,Serial code | Conference |
ISBN | Citations | PageRank |
978-0-7695-4301-7 | 3 | 0.41 |
References | Authors | |
11 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manish Arora | 1 | 166 | 11.88 |
| Jack Sampson | 2 | 398 | 32.45 |
| Nathan Goulding-Hotta | 3 | 163 | 10.26 |
| Jonathan Babb | 4 | 80 | 4.19 |
| Ganesh Venkatesh | 5 | 274 | 17.97 |
| Michael Bedford Taylor | 6 | 1707 | 154.51 |
| Steven Swanson | 7 | 1434 | 82.33 |