Abstract | ||
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Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low. |
Year | DOI | Venue |
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2013 | 10.1109/VTS.2013.6548905 | VTS |
Keywords | DocType | Citations |
important factor,repair mechanism,open defect location,diagnosis resolution,cost-benefit analysis,proposed technique,proposed scheme,open defect,faulty interconnects,design for testability,cost benefit analysis | Conference | 16 |
PageRank | References | Authors |
1.03 | 5 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Lin, Hung-Chih | 1 | 118 | 13.03 |
Wu, Cheng-Wen | 2 | 1843 | 170.44 |
Min-Jer Wang | 3 | 55 | 9.57 |
Chun-Chuan Chi | 4 | 117 | 8.81 |