Name
Title | ||
|---|---|---|
Controlled Placement And Routing Techniques To Improve Timing Balance Of Wddl Designs In Mesh-Based Fpga |
Abstract | ||
|---|---|---|
The Wave Dynamic Differential Logic (WDDL) offers an affective way to address Differential Power Attack (DPA). However, the effectiveness of this countermeasure is guaranteed provided the routing of both the real and complementary paths is balanced, to obtain equal propagation delays and power consumption on differential signals.This paper addresses the problem of timing unbalance. First, we propose dual placement techniques, and quantify the gain that they confer. Then, we introduce a simple but effective new timing-balance driven router based on the PathFinder algorithm.Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 92% in delay balance, while keeping reasonable overhead both in terms of the number of switches used for routing and the critical path delay. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/APCCAS.2010.5774878 | PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS) |
Keywords | Field | DocType |
logic gates,propagation delay,critical path,logic design,network routing,field programmable gate arrays,computer architecture,routing | Logic synthesis,Logic gate,Network routing,Computer science,Field-programmable gate array,Electronic engineering,Power attack,Power consumption | Conference |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Emna Amouri | 1 | 39 | 7.83 |
| Zied Marrakchi | 2 | 152 | 28.68 |
| Habib Mehrez | 3 | 200 | 39.21 |