Name
Abstract | ||
|---|---|---|
Although tree multipliers result in good logic depth, they are not amenable to dense VLSI implementation due to the complexity of wiring. We address the issue of optimal partial product reduction for parallel tree multipliers. An algorithm is developed to trade-off wiring complexity with logic depth. An automatic generator is developed to generate a netlist for any size multiplier with optimized placement information. This netlist with placement information is taken through a datapath place and route tool to create a compact layout for the generated multipliers. The results indicate that the performance of the generated multipliers in terms of speed can be similar to custom designed multipliers |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ICCD.1999.808440 | ICCD |
Keywords | Field | DocType |
recent advance,flexible hardware architecture,parallel tree multipliers,logic cad,trees (mathematics),logic depth,automatic generation,multiplying circuits,compact layout,automatic generator,optimal partial product reduction,route tool,dense vlsi implementation,optimized placement information,system design,placement-driven netlists,tree multiplier generation,datapath place,wiring complexity,process design,logic,minimization,heart,digital signal processing,place and route,very large scale integration | Netlist,Datapath,Computer science,Parallel computing,Place and route,Multiplier (economics),Logic depth,Very-large-scale integration,Partial product reduction | Conference |
ISSN | ISBN | Citations |
1063-6404 | 0-7695-0406-X | 2 |
PageRank | References | Authors |
0.40 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gautam, A.K. | 1 | 2 | 0.40 |
| Visvanathan, V. | 2 | 10 | 3.55 |
| Nandy, S.K. | 3 | 43 | 7.29 |