Name
Abstract | ||
|---|---|---|
This paper proposes a methodology for the development of simple arithmetic self-checking circuits using Signed Digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault set is shown. The main idea underlying the paper is to exploit the properties of Signed Digit representation allowing carry-free operations. In a carry free adder the parity can be easily checked allowing therefore detecting the occurrence of a fault belonging to the considered stuck-at fault set. The proposed architecture is therefore very suitable for the implementation of self-checking adders that are also fast due to the same carry free property. |
Year | Venue | Keywords |
|---|---|---|
2003 | DFT | main idea,stuck-at fault set,parity checker,digit representation,free property,self-checking capability,simple arithmetic,self-checking adder,carry-free operation,digit arithmetic circuit,error detection,proposed architecture,free adder |
Field | DocType | ISSN |
Adder,Computer science,Numerical digit,Arithmetic,Algorithm,Exploit,Error detection and correction,Signed-digit representation,Parity (mathematics),Electronic circuit | Conference | 1550-5774 |
ISBN | Citations | PageRank |
0-7695-2042-1 | 6 | 0.53 |
References | Authors | |
4 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| G. C. Cardarilli | 1 | 71 | 10.34 |
| M. Ottavi | 2 | 166 | 19.26 |
| Salvatore Pontarelli | 3 | 368 | 54.05 |
| Marco Re | 4 | 194 | 35.03 |
| A. Salsano | 5 | 90 | 13.37 |