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Transmission line test structures are stressed at ambient temperatures ranging from 75 to 160 °C and current densities from ∼5 to 7 MA/cm 2 . Failure is considered to have occurred when the resistance increases by 10% over its initial value. Failure times are modeled using Black’s equation and the E a and current density exponent ‘ n ’ are found to be ∼1 eV and ∼2–4, respectively, in agreement with the literature. Predicted FIT rates are found to be negligible easily meeting even the most severe FIT budget. Experimental evidence suggests that the current density used in testing is well above the critical Blech value. Predicted lifetimes at J = 2.3 MA/cm 2 are consistent with observation, indicating that high stress data can be used to predict low stress behavior. 1 Introduction As die sizes continue to shrink in an effort to reduce cost, larger current densities must be carried by transmission lines (TLs). In the III–V semiconductor industry, a common material used in TLs is gold for its low resistivity and high electromigration resistance. Our concern here is to determine the effect of current density and temperature under high stress conditions and extrapolate to low stress (use conditions) in order to find a realistic design rule. To estimate the reliability at use conditions, test structures were stressed at high current and temperature and the resulting data fitted to Black’s equation given by (1a) t f = A · J - n · e E a / kT or alternatively, (1b) ln t f = ln A - n ln J + E a kT where A is a constant, J is the current density, n is the current density exponent 1 The value of n is positive. 1 and E a is the activation energy. Tests were run at constant current, so J was known for each device. The temperature was calculated from temperature coefficient of resistance (TCR) measurements on a set of representative devices. The device was considered to have failed when the resistance increased by 10% over its initial value. 2 Experimental Over 300 test structures consisting of metal layers of Ti/Pt/Au/Ti (∼1 μm thick and 4 μm wide) from three different wafer lots were DC biased at high current densities ranging from ∼5 to 7 MA/cm 2 . The allocation of parts tested across current ambient temperature is summarized in Table 1 . Gold made up the bulk of the metal sandwich. The test structure incorporated 10 turns from cathode to anode with a total length of ∼500 μm (see Fig. 1 ). Within each turn, the line went over a ∼1.5 μm step. The step consisted of a mesa capped by a metal layer. The mesa/metal combination was passivated with silicon nitride prior to deposition of the Ti/Pt/Au/Ti layers. The purpose of the step was to create a stress concentration in the line, approximating what an actual line might see in a real device. This metal sandwich was capped by ∼3 μm of planarized oxide. Accelerated void growth is expected in the presence of these steps [1] . Lifetesting was performed in PE9000A Microburnin test ovens at constant current using Kelvin voltage sensing. The ambient temperatures ranged from 75–160 °C. Devices were mounted in a test card which in turn was inserted in a test slot in the oven. The assignment of devices to cards, positions within the card and oven slots were randomized. TCR measurements were performed on a Micromanipulator probe station with a Temptronics high temperature chuck on eight representative samples. Those parts used for TCR measurements were not part of the stress test. The procedure was as follows. The resistance of the test structure was measured at currents of 5, 10, 25, 50 and 100 mA over a temperature range of 25–300 °C. A plot of the resulting R vs. dissipated power ( P diss ) over temperature is shown in Fig. 2 . The curves were extrapolated to 0 P diss giving the value of resistance with no Joule heating. The ambient temperature for each curve was plotted vs. the y -intercepts, yielding the temperature of the line as a function of resistance ( Fig. 3 ). The resulting equation used to predict the temperature at time t = 0 was: (2) T 0 = - 302.6 + 117.3 · R 0 where R 0 is the initial value of resistance. The temperature coefficient of resistance, β , can be written as (3) β = 1 R 0 · dR dT A typical value of R 0 is ∼2.8 Ω at room temperature so from (2) , β will be 1/(2.8 × 117.3) = 0.003 °C −1 in good agreement with the reported value for pure gold of 0.0034 °C −1 [2] . At the start of the test, R 0 was used to predict the temperature. Since R 0 was slightly different for each device, the stress temperature varied across devices. As the device degraded and resistance went up, so did the temperature. However, the device temperature could no longer be predicted by (2) since the increase in resistance with time was not due to a temperature increase but presumably due to changes in the film microstructure and/or geometry. To determine the temperature of the line for t > 0, the thermal resistance was estimated as follows: (4) R th = T 0 - T amb P diss 0 where T 0 and P diss 0 are estimated from R 0 and R th is assumed fixed as the electrical resistance increases. The relevant temperature of the line was assumed to be at the mid-point between the start of the test and failure, or 5% more than R 0 . So T for the line was: (5) T = T amb + R th · P diss mid where P diss mid is the dissipated power when R = 1.05 R 0 . 3 Results 3.1 Failure mode After stressing, parts were examined optically for damage. Often, cracks were observed in the passivation near a step as would be expected. Fig. 4a is a focused ion beam (FIB) cross-section of such a crack, showing evidence of metal migration and voiding consistent with electromigration. 2 Only some devices received visual inspection prior to the start of the test. However, several different test structures were on the same die along with the type actually tested. Visual inspection of these non-electrically stressed devices did not reveal any cracks, consistent with the assumption that no flaws were present in any structure at the start of the test. 2 This device was stressed at T amb = 105 °C and J = 6.8 MA/cm 2 . Fig. 4b is a close-up of the same region. Note that voiding occurred downwind from the hillock. It is assumed that those voids contributed to a different hillock closer to the anode. Clearly the formation of voids will cause an increase in resistance of the line. Other cross-sections showed evidence of migration in regions far from a step (see Fig. 5 ). Fig. 5a shows the profile of a line with no visible damage. In comparison, Figs. 5b and 5c show cracking in the passivation due to a pile up of metal. This result implies that damage could occur throughout the line and is not concentrated in one segment of the structure. 3.2 Initial analysis Fig. 6 shows a typical plot of %change in R vs. time for 10 devices tested at J ∼ 5.5 MA/cm 2 and T amb = 150 °C. The horizontal line at 10% shows how the failure times were determined. All devices were run to failure so none of the data were censored. The failure times followed a lognormal distribution. The reliability parameter estimates and their associated standard errors for all three wafer lots are given in Table 2 . A separate analysis indicated the difference between lots was significant (results not shown). Therefore, each lot was treated separately. Although parts were tested at 320 mA, it was found that inclusion of these data led to a significant interaction between current and temperature. An interaction between temperature and current implies that a current density could be found where the degradation rate would increase with a decrease in temperature. This result may be due to the presence of a different failure mode at high current density. To avoid this physically unappealing result, the high current data were removed. This exclusion is acceptable since extrapolation will be performed to low current density. The overall least squares fit of the data to Black’s equation is fair. The individual coefficient of determination, R 2 , for each lot is shown in Table 2 . Table 3 gives the parameter estimates with the associated 95% confidence bounds along with the 10 year average FIT rate for each lot. The largest estimated FIT rate at T amb = 125 °C and J = 1 MA/cm 2 is ∼2E−19 with an upper 95% CB of ∼7E−5. 3 Confidence intervals formed using the bootstrap percentile technique. 3 A worst case estimate of the total length of all transmission lines per die is ∼500,000 μm. Assuming this is the equivalent of 1000 test structures, the upper bound of the FIT rate would be 1000 × 7E–5 or 0.07 FITs in 10 years (using the additive property of FITs). So, the failure rate due to TLs is predicted to be miniscule compared to any reasonable FIT budget even under extremely high ambient temperatures and current densities. Similar calculations were performed over temperature and current density to provide a safe operating area. Plots for all three lots are shown in Fig. 7 . Since most of the metal stack is gold, the values of E a and n from Table 2 can be compared to that of pure gold. Other workers have observed values of E a that vary from 0.42 to 0.98 eV [3–6] . These estimates are in fair agreement with the results from the three lots tested. Further, values of n from electromigration studies of gold have been reported to be between −3.3 and 4 [7] , so the present estimates of ∼2–4 are either similar or somewhat conservative. 3.3 Implications of different failure criteria One concern in the above analysis is temperature uniformity. The TCR approach used here measures the average temperature across the line. Under high stress conditions, the temperature may become non-uniform with a gradient developing from the anode or cathode towards the center of the line. A large gradient or hot spot will cause the failure times to be artificially lower than would be expected if the temperature were uniform. On the other hand, the gradient should be smaller at lower stress conditions. Thus, temperature gradients and/or hot spots will tend to bias the reliability parameter estimates. Part of this question was addressed by varying the failure criterion to see its effect on the reliability estimates. If the failure mode changes during stress, then the estimates would be sensitive to choice of failure criterion. Table 4 shows the reliability estimates of the three lots assuming different criteria of failure. In all cases, the temperature of the line was calculated from the resistance measured at the mid-point between t = 0 and failure. Clearly, the values do not show a strong dependence suggesting that the failure mode is constant during stress. Temperature gradients/hot spots would also cause non-uniform damage to the line. From Figs. 4 and 5 , damage is not limited to a few spots but can occur anywhere along the line. Further, the residuals from a fit of Eq. (1b) have a normal distribution implying the failure times are lognormal (see Appendix A ). A lognormal failure distribution is associated with a cumulative degradation mechanism as opposed to a “weakest link” failure mode where many sites are competing to cause failure [8] . The failure times from a weakest link mechanism would likely follow a Weibull distribution. 4 The failure times were fit to a Weibull distribution but the lognormal provided a significantly better fit. 4 Thus, a lognormal distribution would be expected if damage occurred either in one spot only or throughout the line. Since damage is observed in several places, the distribution of the failure times is consistent with a fairly uniform temperature profile. The above assumes the temperature is constant during stress. In reality, the temperature is increasing over time due to increased Joule heating. This situation can be treated as a ramp test where the current density is held fixed and the temperature stress increases. The time to failure at T 0 can be calculated by summing the product of the acceleration factor by the time increment over the temperature history (see Appendix B ). The effect of the varying stress was determined numerically for each device. Table 4 includes that calculation assuming failure occurs at a 10% increase in resistance. Once again, E a , n and s are essentially the same as the previous cases, implying that the temperature along the line is fairly uniform. 3.4 Critical current density As first described by Blech [9] , a critical current density exists below which electromigration should not occur. Black’s equation can be modified to include this effect as shown below: (6) t f = A · ( J - J c ) - n · e E a / kT where J c is the critical current density [10] . Failure to take J c into account can lead to biased estimates and optimistic lifetime extrapolations to use conditions. An attempt was made to estimate J c from the data by the method of maximum likelihood but the estimates were not stable. So, a test was performed at I = 25 mA ( J ∼ 0.6 MA/cm 2 ) and T amb = 150 °C to see if degradation would occur. Fig. 8 shows a plot of %change in R vs. time establishing that R does increase, albeit slowly. Note that an oscillation is observed in the resistance over time. 5 The source of the variation is not clear but may be due to temperature variation over the course of a day. 5 The corresponding variation in the voltage is ∼200 μV. The stated accuracy of the PE9000 in this voltage range is >300 μV. Therefore, the oscillation is within the accuracy of the voltage measurement. From Fig. 8 , the resistance increase can occur in these test structures even at low current density, consistent with electromigration (after ∼2000 h of testing, oxide cracking has not been observed). In fact, electromigration in gold has been reported at 0.6 MA/cm 2 [5] . Since J c is at least an order of magnitude smaller than the current densities used in this test, it will be neglected. 3.5 Predicting at low current density Another 10 devices from lot 2 were stressed at 100 mA ( J = 2.3 MA/cm 2 ) and T amb = 150 °C. The mean value of R 0 was ∼4.17 Ω producing a temperature of 187 °C. Although these parts have been stressed for ∼2000 h, they have degraded by <3% (see Fig. 9 ). Data from lot 2 stressed at conditions given in Table 1 were used to predict the failure time with a failure criterion of 3% increase in R 0 . The predicted MTTF was 12970 h with 95% CB of [2400,69,670]. Extrapolating to the failure criterion, the expected MTTF of the 10 devices is ∼3400 h, consistent with these confidence bounds. This result suggests that these data gathered under high stress can be used to predict behavior under low stress conditions. 4 Summary The effect of temperature and current density on lifetimes of gold based TL test structures were successfully modeled using Black’s equation for three different wafer lots. The values of E a ∼1 eV and n ∼3 for each lot were found to agree well with published values. The estimated reliability at T amb = 125 °C and J = 1 MA/cm 2 was predicted to be quite good. Even the least reliable lot had an estimated upper 95% bound on the 10 year FIT rate of 7E−5. Using the additive property of FITs and assuming an actual transmission line would be the equivalent of 1000 such test structures, the upper bound increased to 0.07 FITs. Thus, the FIT rate can be used to establish a reasonable design rule according to the FIT budget. Low current density ( I = 25 mA) tests were also performed and degradation was observed, consistent with the literature. This suggests that the critical current density, J c , is much less than the current densities used in this investigation and so the effect of J c was neglected. Further, predictions at I = 100 mA assuming 3% degradation gave values that were consistent with extrapolated values. Thus, results from high current testing can be used to predict low current behavior. Appendix A Checking the model An important part of any analysis is to check the assumptions. The major assumptions are: the failure times are lognormal (or equivalently, the logs of the failure times are normal), the shape factor is constant, and no other terms are needed in the model. Since the data are complete, the logs of the failure times can be used and ordinary least squares diagnostics will apply. All analysis discussed here uses the studentized residuals. A plot of lot 2’s studentized residuals are shown in Fig. A.1 . The straight line indicates that the residuals have a normal distribution. A Kolmogorov–Smirnov goodness of fit test also indicated that the distribution was not significantly different than a normal distribution. The constant shape factor assumption was checked graphically by plotting the residuals vs. predicted values in Fig. A.2 . It shows a “scatter shot” appearance consistent with a constant variance. Lastly, a plot of the residuals show no dependence on ln ( J ) or 1/ kT (see Figs. A.3 and A.4 ) indicating that no higher order terms are needed. The same analysis on the other two lots yielded similar results. Since our assumptions have been validated, Black’s equation can be used to make predictions to lower stresses and inferences on those predictions can be trusted. Appendix B Allowing for varying temperature Over time, the temperature of the line will rise since the current is constant and Joule heating increases. If the device is stressed at a particular constant temperature, T , the equivalent amount of stress time at a lower temperature, T 0 , can be estimated using the acceleration factor, AF , given by: (B.1) AF = e E a k · 1 T 0 - 1 T where current density is assumed to be constant. The temperature of the transmission line will be (B.2) T ( t ) = T amb + R th · I 2 · R ( t ) where R is a function of time, R th is constant and the current is fixed at I . The resistance of each device was measured periodically (usually ∼1 min) giving R ( t ). For ease of computation, the temperature increase can be considered a step stress where the temperature is constant between each resistance measurement for time Δ t . Calling the temperature of a device at the start of the test T 0 , the equivalent time at T 0 is found by summing the product of AF and Δ t as below: (B.3) t ( T 0 ) = Δ t 1 + ∑ i = 2 m AF i · Δ t i where t ( T 0 ) is the equivalent time at T 0 , AF i is the i th value of AF calculated using (2) and (B.2) at the i th increment Δ t i and m is the number of measurements of resistance up to failure. Using (B.3) , the equivalent time at T 0 was determined for each device giving a new set of failure times. These were then fit to Black’s equation using maximum likelihood and the resulting estimates are given in Table 4 . References [1] Root BJ, Turner T. Wafer level electromigration tests for production monitoring. In: Proc IRPS; 1985. p. 100–7. [2] R.C. Weast Handbook of chemistry and physics 6th ed. 1983 CRC Press Boca Raton (FL) E-78 [3] Kilgore S et al. Electromigration of electroplated gold interconnects. Mater Res Soc Symp Proc; 863: B8.30.1–6. [4] M. Etzion Study of conductive gold film lifetime under high current densities J Appl Phys 46 4 1975 1455 1458 [5] K.L. Tai M. Ohring Grain-boundary electromigration in thin films. II. Tracer measurements in pure Au J Appl Phys 48 1 1977 36 45 [6] B.J. Klein Electromigration in thin gold films J Phys F: Met Phys 3 1973 691 696 [7] M. Ohring Reliability and failure of electronic materials and devices 1998 Academic Press San Diego (CA) p. 278 [8] P. Tobias D. Trindade Applied reliability 1995 Chapman & Hall New York (NY) p. 90–1 [9] I.A. Blech Electromigration in thin films on titanium nitride J Appl Phys 47 4 1976 1203 1208 [10] Cheng Y-L et al. Back stress model on electromigration lifetime prediction in short length copper interconnects. In: Proc IRPS; 2008. p. 685–6. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1016/j.microrel.2009.02.006 | Microelectronics Reliability |
Keywords | DocType | Volume |
electronics industry,design rules,transmission line,stress,temperature,current density,transmission lines,conductivity,electromigration,gold | Journal | 49 |
Issue | ISSN | ISBN |
5 | Microelectronics Reliability | 0-7908-0120-5 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
1 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Charles S. Whitman | 1 | 8 | 5.83 |