Title
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.
Year
DOI
Venue
2009
10.2197/ipsjtsldm.2.250
IPSJ T. on System LSI Design Methodology
Keywords
DocType
Volume
testing
Journal
2
Citations 
PageRank 
References 
0
0.34
8
Authors
5
Name
Order
Citations
PageRank
Yoshinobu Higami114027.24
Kewal K. Saluja21483141.49
Hiroshi Takahashi314824.32
Sin-ya Kobayashi410.69
Yuzo Takamatsu515027.40