Name
Abstract | ||
|---|---|---|
In recent years, interconnect issues emerged as major performance challenges for Two-Dimensional-Integrated-Circuits (2D-ICs). In this context, Three-Dimensional-ICs (3D-ICs), which consist of several active layers stacked above each other, offer a very attractive alternative to conventional 2D-ICs. However, 3D-ICs also face many challenges associated with the Power Distribution Network (PDN) design due to the increasing power density and larger supply current compared to 2D-ICs. As an important part of 3D-IC PDNs, Power/Ground (P/G) Through-Silicon-Vias (TSVs) should be well-managed. Excessive or ill-placed P/G TSVs impact the power integrity (e.g. IR-drop), and also consume a considerable amount of chip real estate. In this work, we propose a Mixed-Integer-Linear-Programming (MILP)-based technique to plan the P/G TSVs. The goal of our approach is to minimize the average IR-drop while satisfying the total area constraint of TSVs by optimizing the P/G TSV placement. Therefore, the locations, sizes and the total number of the P/G TSVs are co-optimized simultaneously. The experimental results show that the average IR-drop can be reduced by 11.8 % in average using the proposed method compared to a random placement technique with a much smaller runtime. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.7873/DATE.2014.057 | DATE |
Keywords | Field | DocType |
pdn,g tsvs impact,power distribution network,supply current,increasing power density,two-dimensional-integrated-circuits,integrated circuit interconnections,chip real estate,p/g tsv planning,power/ground through-silicon-vias planning,interconnect issues,ir-drop reduction,active layers,power integrity,power density,three-dimensional integrated circuits,integer programming,g tsv placement,linear programming,g tsv planning,planning,total number,random placement technique,total area constraint,si,g tsvs,mixed-integer-linear-programming,average ir-drop,distribution networks,ill-placed p,2d-ic,milp,3d-ic,mathematical model,3d ic,routing,logic gates,optimization | Power network design,Computer science,Distribution networks,Power integrity,Electronic engineering,Chip,Power density,Integer programming,Linear programming,Interconnection | Conference |
ISSN | Citations | PageRank |
1530-1591 | 3 | 0.37 |
References | Authors | |
13 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shengcheng Wang | 1 | 13 | 4.29 |
| Farshad Firouzi | 2 | 275 | 20.28 |
| Fabian Oboril | 3 | 288 | 26.71 |
| Mehdi B. Tahoori | 4 | 1537 | 163.44 |